A communication device, for example, an analog-to-digital converter, which is mounted on a radio device (wireless transmitter and receiver), has a calibration function to prevent its own characteristics from changing, even when there is a change in the environment, such as deviations in manufacturing processes, a fluctuation in temperature, a fluctuation in power supply voltage, or the like.
As one example of the analog-to-digital converter according to the related art, Yun Chiu (Y. Chiu et al., “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE Transactions on Circuits and Systems I Vol. 51, pp. 38-46 (2004) and Takashi Oshima, “Fast Digital Background Calibration for Pipelined Type ADC”, The Institute of Electronics, Information and Communication, Technical Report of IEICE VLD 2006-138, 2007 disclose a background calibration type analog-to-digital converter that uses a reference analog-to-digital conversion unit.
A configuration example of the background calibration type analog-to-digital is shown in FIG. 18. A sample and hold circuit (S/H) 11 repeats the sampling and holding of an input analog signal in synchronization with a CLK signal. A reference analog-to-digital conversion unit 12 and a main analog-to-digital conversion unit 13 are connected to the sample and hold circuit 11 to convert the held voltage values into digital values, and output the converted digital values. An output of M bits of the main analog-to-digital conversion unit 13 is output as an output the calibration type analog-to-digital converter by means of a digital output generating section 14. The digital output generating section 14 performs, for example, an inner product operation of an output code of the main analog-to-digital conversion unit 13 and a weight vector Wi output from a calibration section 15.
The calibration 15 uses the difference between the output of the digital output generating section 14 and the output of the analog-to-digital conversion unit 12 and forms a negative feedback loop that updates a present weight vector Wi on the basis of the difference. As a result, the weight vector Wi is automatically controlled until the output of the digital output generating section 14 is equal to the output of the reference analog-to-digital conversion unit 12, that is, a value where the input analog signal is accurately converted into the digital value. Further, the above-mentioned operation is described in detail in the Takashi Ohshima and therefore, the description thereof will not be repeated.
FIG. 19 shows an example where the background calibration type analog-to-digital converter is mounted on the wireless device. A transmission signal output from a baseband signal processing section 214 is converted into an analog signal by a digital-to-analog converter 215. Then, the interference wave components in the converted analog signal are removed in a filter 29. The output of the filter is multiplied, by a mixer 25, by a local oscillation signal that is generated from a voltage controlled oscillator 26, which is in turn frequency-converted into a transmission frequency. Thereafter, the frequency-converted signal is amplified by an amplifier 23, which is in turn transmitted from an antenna 21. On the other hand, the signal input from the antenna 21 is amplified in a low noise amplifier (LNA) 22, multiplied, by a mixer 24, by the local oscillation signal generated from the voltage controlled oscillator 26, and is frequency-converted into an intermediate frequency. The intermediate frequency is amplified in a variable gain amplifier 27. Then, the interference wave components in the amplified intermediate frequency are removed by a filter 28, which are in turn input to an analog-to-digital converter.
The analog-to-digital converter includes a main analog-to-digital conversion unit 212, a reference analog-to-digital conversion unit 211, a calibration section 213, a digital output generating section, and a sample and hold circuit 210. The operation of the calibration type analog-to-digital converter is the same as the foregoing contents. The output of the background calibration type analog-to-digital converter is input to the baseband signal processing section 214, and then subjected to a process of an upper layer.
On the other hand, the calibration is performed for every MDAC of each stage by setting outputs of a sub ADC within an MDAC for each stage, which configures a pipeline type analog-to-digital conversion section and detects the outputs. A foreground calibration (or self calibration) type analog-to-digital converter is already known in the related art.
Andrew N. Karanicolas, Member, IEEE, Hae-Seung Lee, Senior Member, IEEE, and Kantilal L. Bacrania, Member, IEEE, “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 12, December 1993 discloses a foreground calibration type analog-to-digital converter that corrects a mismatch of a capacitor, an offset of a comparator, charge injection, a finite gain of an op-amp, and nonlinearity of a capacitor, or the like.
B.HERNES, J. Bjornsen, T. Andersen, A. Vinje, H. Korsvoll, F. Telsto, A. Briskemyr, C. Holdo, 0. Moldsvor, “A 92.5 mW 205 MS/s 10b Pipelined IF ADC Implemented in 1.2V/3.3V 0.13 μm CMOS”, Nordic Semiconductor, Trondheim, Norway, 2007 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, Session 25.6, February 2007 and C. Grace, P, Hurst, S. Lewis, “A 12b 80 MS/s Pipelined ADC with Bootstrapped Digital Calibration,” 2004 IEEE International Solid-State Circuits Conference, Session 25.5, February 2004 also disclose a foreground calibration type analog-to-digital converter having the same configuration.
Also, the C. Grace, P, Hurst, S. Lewis discloses a method that uses a dedicated digital-to-analog converter so as to generate a reference analog DC voltage.
Further, JP-A-2004-242028 discloses a method that corrects a relative error in gains between at least two analog-to-digital converters. In other words, in order to correct the relative error in the gains between the analog-to-digital converters, the JP-A-2004-242028 discloses a self regulation method of an AD converter that inputs an output of one digital-to-analog converter to at least two analog-to-digital converter and measures output levels from each analog-to-digital converter so as to regulate the output levels according to the difference when there is the difference between the output levels.